Re: PCI DMA Interrupt latency

[Robert Hancock <hancockr@shaw.ca>]

Burkhard Schölpen wrote:
> Hello,
>
> I'm writing a driver for a custom pci card with an FPGA 
> (Xilinx Spartan 2 (XC2S150-6) with PCI 32 LogiCore), 
> which  can act as a pci bus master. The device is designed 
> to do DMA transfers with high bandwidth. One task is to 
> send image data to a printer which already works quite 
> well, but sometimes there are randomly occuring 
> problems concerning the timing between two DMA 
> transfers. The issue seems to be something like interrupt 
> latency in hardware. Measuring some signals with an 
> oscilloscope shows, that the delay from generating the 
> interrupt, which signals a finished transfer, to the time 
> when the interrupt register on the card is reset (i.e. the 
> beginning of the ISR) sometimes increases to more 
> than 500 microseconds, which is dimensions too high. 

Most likely some driver is disabling interrupts for that period, which 
is really longer than it should be. However, if your card/driver require 
such tight interrupt latency to function correctly, that seems too 
fragile and may not be reliable. Some kind of ringbuffer arrangement 
would likely work better, so that the interrupt does not have to be 
serviced so soon.

--
Robert Hancock      Saskatoon, SK, Canada
To email, remove "nospam" from hancockr@nospamshaw.ca
Home Page: http://www.roberthancock.com/

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