RE: Latency traces I cannot interpret (sa1100, 2.6.15-rc7-rt1)

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On Mon, 2006-01-02 at 15:39 +0100, kus Kusche Klaus wrote:
> > From: Daniel Walker
> > On Mon, 2006-01-02 at 08:57 +0100, kus Kusche Klaus wrote:
> > >   <idle>-0     0D...    1us+: preempt_schedule_irq (svc_preempt)
> > >   <idle>-0     0....    5us!: default_idle (cpu_idle)
> > >   <idle>-0     0D..1 8700us+: asm_do_IRQ (c021da48 1a 0)
> > 
> > Your trace appears to be showing an actual latency of 300us . 
> > The trace
> > starts at 8700us . The default_idle line above is showing 
> > interrupts are
> > enable, and preemption is enabled . So the tracing code 
> > really should be
> > ignoring the default_idle line since there is no reason to be 
> > tracing. 
> Ok, thanks, fine.
> I always thought that the output of the tracer always represents a 
> single block of latency (either interrupts or preemption disabled),
> from its beginning to its end.
> Does that mean that any line with status "0...." is not dangerous
> at all w.r.t. latency?

The tracing isn't correct on ARM . It shouldn't show a max latency of
8700us when it's only 300us . I'm not saying there isn't a problem.

> If this is the case, then it should not only be excluded from the
> trace listing, but also from the total timings! The trace header says
> that this is a latency of 8964 us, and this also means that any
> latency shorter than that is not recorded by the tracer.
> However, if the "real" latency of this trace is only 300 us, there
> are quite likely longer "real" latencies (at least, my own test
> programs strongly indicate that), and I'd like to see their traces
> and get the maximum "real" latency duration in the statistics (the
> interrupt latency histogram is also based on the values in the trace
> and not on the "real" latencies: It has a significant peak around
> 8800 us, and I certainly don't have that many int-off periods of
> 8800 us on my system!).

Right .. I'm still looking into it. ARM is just missing some vital
tracing bits I think .


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