On Fri, Dec 23, 2005 at 03:32:16PM -0600, Jack Steiner wrote:
> On IA64, the "sync" instructions are actually part of the ld.acq ot st.rel
> instructions that are used to set/clear spinlocks.
[...]
> IA64 implements fencing of ld.acq or st.rel instructions as one-directional
> barriers.
So ia64 spin_unlock doesn't do store-store ordering across it. I'm
surprised this is the first time this causes problems. Other architectures
seem to order:
* sparc64 does a membar StoreStore|LoadStore
* powerpc does lwsync or sync, depending on arch
* alpha does an mb();
* x86 is in-order
So, sounds to me like you need to fix your lock primitives, not add
barriers to generic code?
-Olof
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