Sorry Greg, Linus,
I also submitted the two PCI patches on my own with the x86-64
patchkit, hopefully the duplication doesn't cause too much trouble.
Greg KH <[email protected]> writes:
>
> From what I can tell, it's too late in the callstack for us to change
> the read ops for this device to be the other one. The problem is (and
> Andi can correct me if I'm wrong), some boxes basically have incomplete
> MCFG acpi tables (the tables do not describe all PCI busses that are
> present in the box). But we don't realize this until we are about to do
> the read function.
It can happen with perfectly legal MCFG tables. If a bus is not listed
in MCFG then we must fallback to type1. This happens on AMD K8 systems
because the busses in the builtin northbridge don't support mmconfig,
only busses on external bridges do. In theory it could happen on
other systems too (although external northbridges typically support
mmconfig for everything if they do at all)
In addition we have some boxes with broken MCFG tables who don't get
the tables right, this is what the next patch was trying to fix.
> I remember I looked into trying to set this up at probe/init time, and
> it was almost impossible to do so, due to the structure of the code.
Yes, I also didn't see an easy way to do it, although it would be probably DTRT.
-Andi
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