Can't build loadable module for 2.6.kernel

Hi all,

I hope this is the right forum for this question.

I'm trying to build a loadable module for a telephony card that includes several files. Some of the files are source files (written by me) and some are object files (provided by the chip vendor). I'm unable to link the vendor object files with the target.

Make displays the following error:

make[4]: *** No rule to make target `drivers/telephony/mrvphone/apicnt.s', needed by `drivers/telephony/mrvphone/apicnt.o'. Stop.

The makefile has the following rule to build apicnt.o:
apicnt.o: apicnt.o.shipped
   cp apicnt.o.shipped apicnt.o

I have also included the whole Makefile with this email.

Thanks in advance,


Carlos Munoz

#
# Makefile for the phone_mrvl driver loadable module
#
TARGET = phone_mrvl.o

obj-$(CONFIG_PHONE_MARVELL) = phone_mrvl.o

ifeq ($(CONFIG_PHONE_LEGERITY),y)
phone_mrvl-objs = mrvphone.o slic.o legerity.o vp_hal.o sys_service.o apicnt.o apiinit.o apiquery.o vp_api.o vp_api_common.o mvutils.o
endif

ifeq ($(CONFIG_PHONE_PROSLIC),y)
phone_mrvl-objs = mrvphone.o proslic.o
endif

CFLAGS += -D__linux__
EXTRA_CFLAGS += -Idrivers/telephony/mrvphone
EXTRA_CFLAGS += -DNDEBUG -Dlinux -D__linux__ -Dunix -DEMBED -DLINUX -DHOST_LE

ifeq ($(CONFIG_PHONE_LEGERITY),y)
EXTRA_CFLAGS += -D__LEGERITY__
endif
ifeq ($(CONFIG_PHONE_PROSLIC),y)
EXTRA_CFLAGS += -D__PROSLIC__
endif

all: $(TARGET)

$(TARGET): $(OBJS)
	$(LD) -r $(OBJS) -o $(TARGET)

clean:
	-rm -f $(TARGET) *.elf *.gdb *.o

apicnt.o: apicnt.o.shipped
	cp apicnt.o.shipped apicnt.o

---

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