Hi Andi,
On Tue, 29 Nov 2005, Andi Kleen wrote:
> I'm considering to enable CR4.PCE by default on x86-64/i386. Currently it's 0
> which means RDPMC doesn't work. On x86-64 PMC 0 is always programmed
> to be a cycle counter, so it would be useful to be able to access
> this for measuring instructions. That's especially useful because RDTSC
> does not necessarily count cycles in the current P state (already
> the case on Intel CPUs and AMD's future direction seems to also
> to decouple it from cycles) Drawback is that it stops during idle, but
> that shouldn't be a big issue for normal measuring. It's not useful
> as a real timer anyways.
Some processor implementations don't have a performance counter which
ticks during the idle thread either.
> Any comments on this?
I think that this should be best left to a profiling tool to configure and
not a general kernel facility. I also have very little faith in processor
vendors not doing to performance counters what was done to the TSC.
Zwane
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