Andi Kleen writes:
> Hallo,
>
> I'm considering to enable CR4.PCE by default on x86-64/i386. Currently it's 0
> which means RDPMC doesn't work. On x86-64 PMC 0 is always programmed
> to be a cycle counter, so it would be useful to be able to access
> this for measuring instructions. That's especially useful because RDTSC
> does not necessarily count cycles in the current P state (already
> the case on Intel CPUs and AMD's future direction seems to also
> to decouple it from cycles) Drawback is that it stops during idle, but
> that shouldn't be a big issue for normal measuring. It's not useful
> as a real timer anyways.
>
> On Pentium 4 it also has the advantage that unlike RDTSC it's not
> serializing so should be much faster.
>
> The kernel change would be to always set CR4.PCE to allow RDPMC
> in ring 3.
>
> It would be actually a good idea to disable RDTSC in ring 3 too
> (because user space usually doesn't have enough information to make
> good use of it and gets it wrong), but I fear that will break
> too many applications right now.
PMC0 stops being a cycle counter as soon as any real driver
(not the NMI watchdog) takes over the hardware, such as oprofile,
perfmon2, or perfctr. So user-space cannot rely on the semantics
of PMC0. I have no objection to globally enabling CR4.PCE.
Disabling user-space RDTSC (setting CR4.TSD) seems evil and pointless.
At least some users of it (the perfctr library and I hope eventually
also perfmon2) do use it in an SMP-safe manner (through special
user/kernel protocols).
/Mikael
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