On Mon, Nov 28, 2005 at 12:39:28PM -0500, Lee Revell wrote:
> On Mon, 2005-11-28 at 09:30 -0800, [email protected] wrote:
> > The kernel's use of TSC is wholly incorrect. TSCs can ramp up and
> > down and *do* vary between nodes as well as between cores within a
> > node. You really can not compare TSCs between cpu cores at all, as is
> > (and the kernel assumes 1 global TSC in at least a few places).
>
> That's one way to look at it; another is that the AMD dual cores have a
> broken TSC implementation. The kernel's use of the TSC was never a
> problem in the past...
Sure. But the OS can be fixed, the chips can not. That said, I'd like to
see a spec that says TSCs are a) synced, b) linear. If such a beast
exists, then we can all mock AMD publicly. If not, we should hush up and
fix the parts that can be fixed.
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