John Bowler wrote:
+/* On a little-endian IXP4XX system (tested on NSLU2) contrary to the
+ * Intel documentation LDRH/STRH appears to XOR the address with 10b.
I don't think this is correct. i.e., I think the Intel docmentation is
correct.
The Application Note on IXP4xx endianess operation[1] says that (by
default) the XScale core operates in address coherency mode (i.e., it
flips address bits). I suspect you need to set BYTE_SWAP_EN in
EXP_CNFG1 and use the P bit in the MMU to get data coherency mode for
various peripherals (probably all expansion bus periperals and possibly
all the APB peripherals).
Also, I've noticed that the PCI_CSR is mis-configured when the XScale
core is in little-endian mode. ABE (AHB is big-endian) /must/ always be
set -- remember that the NPEs are always big-endian devices.
Since I'd never run an IXP4xx in little-endian mode I've not looked at
this issue in any great depth so I could be wrong here. Regardless, the
proposed hack to the flash map driver is wrong since all expansion bus
peripherals are affected not just flash (i.e., the solution needs to be
more generic rather than flash driver specific).
David Vrabel
[1] http://www.intel.com/design/network/applnots/25423701.pdf
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