Re: [PATCH]: Handling spurious page fault for hugetlb region for 2.6.14-rc4-git5

[Linus Torvalds <torvalds@osdl.org>]

On Wed, 19 Oct 2005, Rohit Seth wrote:
> 
> IA-64 can prefetch any entry from VHPT (last level page table)
> irrespective of its value.  You are right that i386 and x86_64 does not
> cache !present entry.  Though OS is suppose to handle those faults if
> happen.

Well.. 

The fact is, the VM layer is designed for systems that do not cache 
not-present entries in their TLB. See for example the end of do_no_page() 
in mm/memory.c:

	        /* no need to invalidate: a not-present page shouldn't be cached */
	        update_mmu_cache(vma, address, entry);
	        lazy_mmu_prot_update(entry);
	        spin_unlock(&mm->page_table_lock);
	out:
	        return ret;

which _allows_ for hardware that caches not-present pages, but the 
architecture needs to catch them in the "update_mmu_cache()".

IOW, the kernel is largely designed for present-only caching, and only has 
explicit tlb flush macros for that case.

If ia64 caches non-present TLB entries, then that would seem to be a bug 
in the Linux ia64 port:

 - include/asm-ia64/pgtable.h:
	#define update_mmu_cache(vma, address, pte) do { } while (0)

(Of course, you can and maybe do handle it differently: you can also 
decide to just take the TLB fault, and flush the TLB at fault time in your 
handler. I don't see that either on ia64, though. Although I didn't look 
into any of the asm code, so maybe it's hidden somewhere there).

			Linus
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