On Sat, Oct 15, 2005 at 11:02:48PM +0200, Stefan Richter wrote:
> What about the PCI_CACHE_LINE_SIZE read/write?
>
> Jody McIntyre wrote on 2005-02-09:
> | Can you try the fix without
> | pci_write_config_word(dev,PCI_CACHE_LINE_SIZE,toshiba_pcls);
> | or pci_read_config_word(dev,PCI_CACHE_LINE_SIZE,&toshiba_pcls);
> | and report if it still works?
> |
> | If it doesn't work, try leaving those lines out but adding
> | pci_clear_mwi(dev);
> | after the mdelay(), on the off chance that the device thinks mwi is on.
> |
> | The correct fix for this, if possible, is actually a pci quirk instead
> | of the dmi-based approach, but if reading PCI_CACHE_LINE_SIZE before
> | pci_enable_device() really is necessary, this will be rather difficult.
> [ http://marc.theaimsgroup.com/?l=linux1394-devel&m=110797909807519 ]
It looks like it is.
I removed the PCI_CACHE_LINE_SIZE read and write, and that didn't work.
I added in a pci_clear_mwi(dev) and that didn't work either. It looks
like the whole patch that I posted earlier is required.
Thanks,
Jesse
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