Nick Piggin <[email protected]> wrote:
>
> Well yes, that's on the store side (1, above). However can't a CPU
> still speculatively (eg. guess the branch) load the page->flags
> cacheline which might be satisfied from memory before the page->count
> cacheline loads? Ie. you can still have the correct write ordering
> but have incorrect read ordering?
>
> Because neither PageDirty nor page_count is a barrier, and there is
> no read barrier between them.
Yes you're right. A read barrier is required here.
I think Ben was actually agreeing with you. He's just questioning
whether the corresponding write barrier existed on CPU 1 (the answer
to which is affirmative).
Cheers,
--
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