Re: Fwd: Telecom Clock Driver for MPCBL0010 ATCA computer blade

[Alexey Dobriyan <adobriyan@gmail.com>]

> --- linux-2.6.14-rc2-mm2/drivers/char/tlclk.c
> +++ linux-2.6.14-rc2-mm2-tlclk/drivers/char/tlclk.c

Can you drop ioctl part of interface and leave only sysfs one?

> +#ifdef TLCLK_IOCTL
> +static int
> +tlclk_ioctl(struct inode *inode,
> +	    struct file *filp, unsigned int cmd, unsigned long arg)
> +{
> +	unsigned long flags;
> +	unsigned char val;
> +	int ret_val = 0;
> +
> +	val = (unsigned char)arg;
> +	if (_IOC_TYPE(cmd) != TLCLK_IOC_MAGIC)
> +		return -ENOTTY;
> +
> +	if (_IOC_NR(cmd) > TLCLK_IOC_MAXNR)
> +		return -ENOTTY;
> +
> +	spin_lock_irqsave(&event_lock, flags);
> +	switch (cmd) {
> +	case IOCTL_RESET:
> +		SET_PORT_BITS(TLCLK_REG4, 0xfd, val);
> +		break;
> +	case IOCTL_MODE_SELECT:
> +		SET_PORT_BITS(TLCLK_REG0, 0xcf, val);
> +		break;
> +	case IOCTL_REFALIGN:
> +		/* GENERATING 0 to 1 transistion */
> +		SET_PORT_BITS(TLCLK_REG0, 0xf7, 0);
> +		udelay(2);
> +		SET_PORT_BITS(TLCLK_REG0, 0xf7, 0x08);
> +		udelay(2);
> +		SET_PORT_BITS(TLCLK_REG0, 0xf7, 0);
> +		break;
> +	case IOCTL_HARDWARE_SWITCHING:
> +		SET_PORT_BITS(TLCLK_REG0, 0x7f, val);
> +		break;
> +	case IOCTL_HARDWARE_SWITCHING_MODE:
> +		SET_PORT_BITS(TLCLK_REG0, 0xbf, val);
> +		break;
> +	case IOCTL_FILTER_SELECT:
> +		SET_PORT_BITS(TLCLK_REG0, 0xfb, val);
> +		break;
> +	case IOCTL_SELECT_REF_FREQUENCY:
> +		SET_PORT_BITS(TLCLK_REG1, 0xfd, val);
> +		break;
> +	case IOCTL_SELECT_REDUNDANT_CLOCK:
> +		SET_PORT_BITS(TLCLK_REG1, 0xfe, val);
> +		break;
> +	case IOCTL_SELECT_AMCB1_TRANSMIT_CLOCK:
> +		if ((val == CLK_8kHz) || (val == CLK_16_384MHz)) {
> +			SET_PORT_BITS(TLCLK_REG3, 0xf8, 0x5);
> +			SET_PORT_BITS(TLCLK_REG1, 0xfb, ~val);
> +		} else if (val >= CLK_8_592MHz) {
> +			SET_PORT_BITS(TLCLK_REG3, 0xf8, 0x7);
> +			switch (val) {
> +			case CLK_8_592MHz:
> +				SET_PORT_BITS(TLCLK_REG0, 0xfc, 1);
> +				break;
> +			case CLK_11_184MHz:
> +				SET_PORT_BITS(TLCLK_REG0, 0xfc, 0);
> +				break;
> +			case CLK_34_368MHz:
> +				SET_PORT_BITS(TLCLK_REG0, 0xfc, 3);
> +				break;
> +			case CLK_44_736MHz:
> +				SET_PORT_BITS(TLCLK_REG0, 0xfc, 2);
> +				break;
> +			}
> +		} else
> +			SET_PORT_BITS(TLCLK_REG3, 0xf8, val);
> +		break;
> +	case IOCTL_SELECT_AMCB2_TRANSMIT_CLOCK:
> +		if ((val == CLK_8kHz) || (val == CLK_16_384MHz)) {
> +			SET_PORT_BITS(TLCLK_REG3, 0xc7, 0x28);
> +			SET_PORT_BITS(TLCLK_REG1, 0xfb, ~val);
> +		} else if (val >= CLK_8_592MHz) {
> +			SET_PORT_BITS(TLCLK_REG3, 0xc7, 0x38);
> +			switch (val) {
> +			case CLK_8_592MHz:
> +				SET_PORT_BITS(TLCLK_REG0, 0xfc, 1);
> +				break;
> +			case CLK_11_184MHz:
> +				SET_PORT_BITS(TLCLK_REG0, 0xfc, 0);
> +				break;
> +			case CLK_34_368MHz:
> +				SET_PORT_BITS(TLCLK_REG0, 0xfc, 3);
> +				break;
> +			case CLK_44_736MHz:
> +				SET_PORT_BITS(TLCLK_REG0, 0xfc, 2);
> +				break;
> +			}
> +		} else
> +			SET_PORT_BITS(TLCLK_REG3, 0xc7, val << 3);
> +		break;
> +	case IOCTL_TEST_MODE:
> +		SET_PORT_BITS(TLCLK_REG4, 0xfd, 2);
> +		break;
> +	case IOCTL_ENABLE_CLKA0_OUTPUT:
> +		SET_PORT_BITS(TLCLK_REG2, 0xfe, val);
> +		break;
> +	case IOCTL_ENABLE_CLKB0_OUTPUT:
> +		SET_PORT_BITS(TLCLK_REG2, 0xfd, val << 1);
> +		break;
> +	case IOCTL_ENABLE_CLKA1_OUTPUT:
> +		SET_PORT_BITS(TLCLK_REG2, 0xfb, val << 2);
> +		break;
> +	case IOCTL_ENABLE_CLKB1_OUTPUT:
> +		SET_PORT_BITS(TLCLK_REG2, 0xf7, val << 3);
> +		break;
> +	case IOCTL_ENABLE_CLK3A_OUTPUT:
> +		SET_PORT_BITS(TLCLK_REG3, 0xbf, val << 6);
> +		break;
> +	case IOCTL_ENABLE_CLK3B_OUTPUT:
> +		SET_PORT_BITS(TLCLK_REG3, 0x7f, val << 7);
> +		break;
> +	case IOCTL_READ_ALARMS:
> +		ret_val = (inb(TLCLK_REG2) & 0xf0);
> +		break;
> +	case IOCTL_READ_INTERRUPT_SWITCH:
> +		ret_val = inb(TLCLK_REG6);
> +		break;
> +	case IOCTL_READ_CURRENT_REF:
> +		ret_val = ((inb(TLCLK_REG1) & 0x08) >> 3);
> +		break;
> +	}
> +	spin_unlock_irqrestore(&event_lock, flags);
> +
> +	return ret_val;
> +}
> +#endif

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