TR : 440bx and natsemi

[Frédéric POTTER <fpotter@cirpack.com>]

    Hi, 

    We have designed an embedded board, based on Celeron ULV 400 Mhz and 440bx chipset.
    The BIOS has been derivated from Linux Bios of the 440mx (mx and bx have minimal differences).
    The ethernet devices are natsemi DP83816 (latest HW revision)

The issue : 
----------------

    If we set the L1 CPU cache in write back mode then, under heavy ethernet load, we have various memory
corruption on the host memory. It looks like, basically, the natsemi device, when getting bus master, is 
accessing former skbuf physicall adresses in the tx_ring structure, and therefore writing at various location
in the memory, generating various kernel panic a few moment later.

    If we set the L1 CPU cache in write through, the issue vanishes completely (even after a few days of heavy
load)..

    Since we have designed this whole system (hardware, BIOS etc..), it may clearly be that we have introduced
a cache coherency issue in the system, but we have checked it all, and it seems like not
    * snooping HW interface is present, correctly wired
    * Intel CPU and chipset seems to be properly configured, and anyway no configuration seems to be present
that would have allowed us to 'disable' cache coherency.
    * No Intel CPU or chipset errata have been found that refers to cache snooping issues.

Does anyone have a clue on this one ? Does someone have a 440bx with a Natsemi device (that may be a rare
configuration BTW, since 440bx is used in laptop where the natsemi is fairly rare) 
Are we just discovering an N+1 Intel issue or did we miss something ?

thanks in advance

fred
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/