On Mon, Sep 26, 2005 at 02:59:56PM -0700, Venkatesh Pallipadi wrote:
> The code that prints the cache size assumes that L3 always lives in chipset and
> is shared across CPUs. Which is not really true.
>
> I think all the cachesizes reported by cpuid are in the processor itself.
> The attached patch changes the code to reflect that.
>
> Dave, any idea where that original comment in the code came from?
Been there for a long time iirc (Though I've not checked [my kingdom for
a 'git annotate' tool])
> Are there any
> systems which reports the L3 cache size in cpuid, when L3 sits in northbridge?
Very unlikely.
The only legacy system with L3 that I recall was the AMD K6-III (which had on-CPU L1/L2,
though some motherboards at the time also included an L3 (or L2 if used with an earlier
socket 7 cpu). None of those off-cpu caches were detectable with cpuid, and
required reading from pci config space to determine their size/status etc.
The big question I have though is how relevant that 'weighting' is today
if we factor in L3.
Dave
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