Andi Kleen <[email protected]> wrote:
>
> On Wed, Sep 21, 2005 at 10:15:08AM -0500, Ray Bryant wrote:
> > On Tuesday 20 September 2005 23:03, Daniel Jacobowitz wrote:
> >
> > >
> > > FYI, at least I have reproduced this without powernow loaded.
> >
> > There are cases that we are aware of where the TSC will count slower while the
> > processor is halted. This can make TSC's get out of sync on dual cores.
You mean a single `hlt' instruction? I guess that rules out resyncing them.
> Ok thanks for the confirmation. I guess John's patch is ok then.
> Drawback is much slower to extremly slow gettimeofday (depending
> if the chipset/BIOS has usable HPET, most seem not to)
That's a really big drawback. Will this affect many CPU types?
If the user was prepared to use `idle=poll' then they could get their fast
gettimeofday() back, perhaps.
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