On Thu, 8 Sep 2005, Andy Fleming wrote:
The new PHY Layer (drivers/net/phy/*) can provide all these features
for you without much difficulty, I suspect.
As pointed to be Andrew a few days ago, this driver supports a lot of
chips - for most of them the test hardware would be hard to come by
and the documentation even more. Unless you'd like to do it based on
"whoever is interested should cry loud"...
The layer supports handling the interrupts for you, or (if it's
shared with your controller's interrupt)
Yes, there is only one interrupt that for data transmission (both Tx
and Rx), statistics, errors and (for those chips that support it) link
state change.
Is the cost of an extra read every minute really too high?
You probably didn't look at the code. The MII registers are not
exposed in the PCI space, they need to be accessed through a serial
protocol, such that each MII register read is in fact about 200 (in
total) of outw and inw/inl operations.
--
Bogdan Costescu
IWR - Interdisziplinaeres Zentrum fuer Wissenschaftliches Rechnen
Universitaet Heidelberg, INF 368, D-69120 Heidelberg, GERMANY
Telephone: +49 6221 54 8869, Telefax: +49 6221 54 8868
E-mail: [email protected]
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