Andi Kleen wrote:
Alan Cox <[email protected]> writes:
On Gwe, 2005-09-02 at 16:29 +1000, Nick Piggin wrote:
2/7
Implement atomic_cmpxchg for i386 and ppc64. Is there any
architecture that won't be able to implement such an operation?
i386, sun4c, ....
Actually we have cmpxchg on i386 these days - we don't support
any SMP i386s so it's just done non atomically.
Yes, I guess that's what Alan must have meant.
This atomic_cmpxchg, unlike a "regular" cmpxchg, has the advantage
that the memory altered should always be going through the atomic_
accessors, and thus should be implementable with spinlocks.
See for example, arch/sparc/lib/atomic32.c
At least, that's what I'm hoping for.
Yeah quite a few. I suspect most MIPS also would have a problem in this
area.
cmpxchg can be done with LL/SC can't it? Any MIPS should have that.
Yes, and indeed it does. However it also tests for "cpu_has_llsc",
but I suspect that SMP isn't supported on those CPUs without ll/sc,
and thus an atomic_cmpxchg could be emulated by disabling interrupts.
Nick
--
SUSE Labs, Novell Inc.
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