* Zwane Mwaikambo <[email protected]> [050809 07:17]:
> On Mon, 8 Aug 2005, Tony Lindgren wrote:
>
> > As far as I remember enabling AMD stop grant disconnects all cpus. This
> > means the system won't be able to do any work until the dyntick timer
> > interrupt wakes up the system.
> >
> > > Both requirements (idling all CPUs together vs individually) I think
> > > will make the patch more complex. Are such systems (which require having to
> > > idle all CPUs together) pretty common that we have to care about?!
> >
> > Probably all AMD SMP based systems? Somebody with better knowledge should
> > verify this.
>
> It would be the K7 only.
OK, still quite a few systems.
> > > But that may be too late on some CPUs. If dyn_tick->skip = 100, all
> > > CPUs skip 100 ticks. However some CPUs may have timers that need to be
> > > service much before that.
> >
> > Not in the current case, as the system is completely idle until some
> > interrupt wakes up the system. Of course it would be different if you make
> > it per-CPU.
>
> I once did a weekend version of this with SMP support and for the PIT, i
> had the last cpu to enter idle turn reprogram the PIT. Unfortunately this
> means waiting for all processors and isn't as effective as a result.
>
> > Well we need to be able to do various things in the idle loop depending on
> > the length of the estimated sleep. For example, if next_timer_interrupt is
> > 2 jiffies away, we cannot do much. But if next_timer_interrupt is 2 seconds
> > away, we can idle pretty much all devices.
> >
> > > > But in any case on P4 systems the APIC timer is not the bottleneck as
> > > > stopping or reprogramming PIT also kills APIC. (This does not happen on P3
> > > > systems). So the bottleneck most likely is the length of PIT.
> > >
> > > On these systems, do you disabled APIC (dyntick=noapic)?
> >
> > Yeah. It only seems to work on P3 systems.
>
> Odd, does reprogramming the APIC at that point get it going again?
Hmmm, might be worth trying.
Tony
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