On Mon, 8 Aug 2005, Benjamin Herrenschmidt wrote:
> On Mon, 2005-08-08 at 02:06 +0200, Bodo Eggert wrote:
> > The wrong values are constant across reboots (see my first mail), and I
> > have a CRT.
> >
> > Can you tell me where the timing values are read?
>
> radeon_write_mode() programs the mode. The monitor timing infos are read
> by the various bits of code in radeon_monitor.c
>
> I'd be curious if you could identify what bit of code is misbehaving
I added preempt_*able around radeon_probe_i2c_connector, and now I get the
output from below and still no sync. Obviously you shouldn't msleep in
preempt-disabled code. I'll try voluntary preemption, but that will at
best hide the error.
Maybe I can mess with the msleep()s like thorndike's cat, but any success
will be an accident.
Aug 9 20:58:26 be1 __mod_timer+0xb4/0x100
Aug 9 20:58:27 be1 [<c04019b1>] schedule_timeout+0x51/0xa0
Aug 9 20:58:27 be1 [<c011ff60>] process_timeout+0x0/0x10
Aug 9 20:58:27 be1 [<c012031f>] msleep+0x2f/0x40
Aug 9 20:58:27 be1 [<c02a3aca>] radeon_probe_i2c_connector+0xaa/0x320
Aug 9 20:58:27 be1 [<c02a1da2>] radeon_probe_screens+0x482/0x5d0
Aug 9 20:58:27 be1 [<c0298689>] radeonfb_pci_register+0x309/0x570
...
Aug 9 20:58:27 be1 scheduling while atomic: swapper/0x00000001/1
Aug 9 20:58:27 be1 [<c0400ed9>] schedule+0x589/0x640
Aug 9 20:58:27 be1 [<c011f492>] lock_timer_base+0x32/0x70
Aug 9 20:58:27 be1 [<c011f584>] __mod_timer+0xb4/0x100
Aug 9 20:58:27 be1 [<c04019b1>] schedule_timeout+0x51/0xa0
Aug 9 20:58:27 be1 [<c011ff60>] process_timeout+0x0/0x10
Aug 9 20:58:27 be1 [<c012031f>] msleep+0x2f/0x40
Aug 9 20:58:27 be1 [<c02a3aca>] radeon_probe_i2c_connector+0xaa/0x320
Aug 9 20:58:27 be1 [<c02a1da2>] radeon_probe_screens+0x482/0x5d0
Aug 9 20:58:27 be1 [<c0298689>] radeonfb_pci_register+0x309/0x570
Aug 9 20:58:27 be1 [<c0281318>] __pci_device_probe+0x48/0x60
--
It is still called paranoia when they really are out to get you.
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