"extern inline" doesn't make much sense.
Signed-off-by: Adrian Bunk <[email protected]>
---
include/asm-i386/div64.h | 2 +-
include/asm-i386/processor.h | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
--- linux-2.6.13-rc3-mm1-full/include/asm-i386/div64.h.old 2005-07-26 01:38:12.000000000 +0200
+++ linux-2.6.13-rc3-mm1-full/include/asm-i386/div64.h 2005-07-26 01:38:20.000000000 +0200
@@ -35,7 +35,7 @@
*/
#define div_long_long_rem(a,b,c) div_ll_X_l_rem(a,b,c)
-extern inline long
+static inline long
div_ll_X_l_rem(long long divs, long div, long *rem)
{
long dum2;
--- linux-2.6.13-rc3-mm1-full/include/asm-i386/processor.h.old 2005-07-26 01:38:28.000000000 +0200
+++ linux-2.6.13-rc3-mm1-full/include/asm-i386/processor.h 2005-07-26 01:38:57.000000000 +0200
@@ -665,7 +665,7 @@
However we don't do prefetches for pre XP Athlons currently
That should be fixed. */
#define ARCH_HAS_PREFETCH
-extern inline void prefetch(const void *x)
+static inline void prefetch(const void *x)
{
alternative_input(ASM_NOP4,
"prefetchnta (%1)",
@@ -679,7 +679,7 @@
/* 3dnow! prefetch to get an exclusive cache line. Useful for
spinlocks to avoid one state transition in the cache coherency protocol. */
-extern inline void prefetchw(const void *x)
+static inline void prefetchw(const void *x)
{
alternative_input(ASM_NOP4,
"prefetchw (%1)",
-
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