Re: Real-Time Preemption, -RT-2.6.12-final-V0.7.51-08

[William Weston <weston@sysex.net>]

On Wed, 6 Jul 2005, Ingo Molnar wrote:

> do the 51-02 (and later) kernels work on the UP Athlon box?

Hi Ingo,

-51-06 and -51-08 are looking stable on the UP Athlon box with the
following patch which causes edge triggered hardirqs to be masked when
pending _and/or_ disabled (instead of both pending _and_ disabled) and
backs out a change from -50-44 that prevents pending edge triggered irqs
from being unmasked:

--- linux.orig/arch/i386/kernel/io_apic.c	2005-07-06 11:08:39.000000000 -0700
+++ linux/arch/i386/kernel/io_apic.c	2005-07-07 03:40:37.000000000 -0700
@@ -1949,8 +1949,7 @@
 static void ack_edge_ioapic_irq(unsigned int irq)
 {
 	move_irq(irq);
-	if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
-					== (IRQ_PENDING | IRQ_DISABLED))
+	if (irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
 		mask_IO_APIC_irq(irq);
 	ack_APIC_irq();
 }
@@ -1997,8 +1996,6 @@
 	unsigned long v;
 	int i;
 
-	if (!(irq_desc[irq].status & IRQ_DISABLED))
-		unmask_IO_APIC_irq(irq);
 /*
  * It appears there is an erratum which affects at least version 0x11
  * of I/O APIC (that's the 82093AA and cores integrated into various
--- linux.orig/kernel/irq/manage.c	2005-07-06 11:08:40.000000000 -0700
+++ linux/kernel/irq/manage.c	2005-07-07 01:04:38.000000000 -0700
@@ -434,6 +434,8 @@
 		 * The ->end() handler has to deal with interrupts which got
 		 * disabled while the handler was running.
 		 */
+		if (!(desc->status & IRQ_DISABLED))
+			desc->handler->enable(irq);
 		desc->handler->end(irq);
 	}
 	spin_unlock_irq(&desc->lock);

The first chunk is based on my understanding of the comments in io_apic.c,
and is not necessary to keep the UP Athlon box stable.  Is my logic OK 
here, or am I missing something really important?

Without the last two chunks of this patch, the UP Athlon box locks up hard
as soon as jackd is started up.

Best Regards,
--ww
-
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