"Richard B. Johnson" <[email protected]> writes:
> Yep. The board uses a PLX PCI 9656BA chip configured for local-bus
> transfers during DMA The local-bus is 32-bits from a FIFO. There
> is no way to collapse these writes from the 32-bit source/dest.
> The transfers are 32 quadwords for a write and 16 quadwords for
> a read, but that represents a burst, not the data-width. Without
> a 64-bit data-path to memory on one side, and a 64-bit data-path
> to the device (a FIFO) on the other side, you will not get 64-bit
> transfers.
I don't know about this particular bridge, but in general you can
have 64-bit transfers over PCI(-X) corresponding to 32-bit transfers
over local bus. The local bus has to be twice as fast as PCI bus or
you won't be able to saturate PCI bus. Especially if it's the bridge
doing PCI BM DMA transfers (and not, say, another processor on the
local bus).
--
Krzysztof Halasa
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