Greg> I've also seen some complaints that it is very arch specific
Greg> (x86 based). But as no other arches seem to want to support
Greg> MSI, I don't really see any need to split it up. Any
Greg> comments about this?
Grant> IA64 supports MSI/MSI-X. Roland, didn't PPC as well?
Grant> I don't think it's *that* x86 specific. The base address
Grant> of the Processor interrupt Block (IIRC 0xfee0000) is
Grant> implemented the same on several arches AFAIK. Even on some
Grant> parisc chipsets. I been constantly chasing other basic
Grant> issues on parisc and just haven't had time to implement it
Grant> in the past 3 years.
Some PPC does support MSI. For example the PCI-X host bridge inside
the IBM (now AMCC) PPC 440GP supports MSI. I don't know if any
non-embedded PPC or PPC64 supports MSI though -- for example do any
IBM POWER-based systems support MSI??
The current code isn't exactly x86-specific. It's more Intel APIC
specific, which means that chipsets that for some reason or another
support the same address/message format will work. So ia64 works as
well. Following from that, HP parisc boxes that use the same chipset
as HP ia64 boxes have a chance at working.
But the PPC 440GP uses a different address and a different message
format. So if anyone cared about supporting that, the current code
would have to be made more generic.
- R.
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