On Sun, 2005-06-05 at 19:05 +0200, Dominik Brodowski wrote:
> On Fri, Jun 03, 2005 at 08:24:35AM -0700, john stultz wrote:
> > On Thu, 2005-06-02 at 19:50 -0400, Parag Warudkar wrote:
> > > On Thursday 02 June 2005 19:20, john stultz wrote:
> > > > Could you see if the slowness you're feeling is correlated to the
> > > > acpi_pm timesource?
> > >
> > > Speaking of which, the below code from arch/i386/timer_pm.c looks particularly
> > > more taxing to me - 3 times read from ioport in a loop - not sure how many
> > > time that executes.
> > >
> > > static inline u32 read_pmtmr(void)
> > > {
> > > u32 v1=0,v2=0,v3=0;
> > > /* It has been reported that because of various broken
> > > * chipsets (ICH4, PIIX4 and PIIX4E) where the ACPI PM time
> > > * source is not latched, so you must read it multiple
> > > * times to insure a safe value is read.
> > > */
> > > do {
> > > v1 = inl(pmtmr_ioport);
> > > v2 = inl(pmtmr_ioport);
> > > v3 = inl(pmtmr_ioport);
> > > } while ((v1 > v2 && v1 < v3) || (v2 > v3 && v2 < v1)
> > > || (v3 > v1 && v3 < v2));
> > >
> > > Shouldn't that loop be limited to the broken chipsets - why would correct
> > > people with correctly working chipsets carry this extra burden? (Or is it
> > > insignificant?)
> >
> > Yea, that would be nice to only do the triple read on the affected
> > systems. Although outside of the comment I don't have any real data as
> > to which system suffer from the issue.
>
> IIRC (from the comment above) several chipsets suffer from this
> inconsistency, namely the widely used PIIX4(E) and ICH(4 only? or also other
> ICH-ones?). Therefore, we'd need at least some sort of boot-time check to
> decide which method to use... and based on the method, we can adjust the
> priority maybe?
Well, I'm not sure if this would be reasonably auto-detectable by just
reading the pmtmr in a loop. That could take awhile. But some form of
DMI blacklist should cover us. Ok, I'll work on this for the next
release.
thanks
-john
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