William Lee Irwin III wrote:
On Fri, Jun 03, 2005 at 05:50:55PM -0700, Subrahmanyam Ongole wrote:
When we run our application on AMD Opteron processors, we are seeing a
large number of L1_AND_L2_DTLB_MISSES. We used oprofile to measure
these numbers.
[...]
PAGE_SIZE at the moment is intimately tied to the MMU's notions of
address translation, which are determined by hardware.
And even if we were able to increase the PAGE_SIZE that
the kernel uses, this wouldn't really help your TLB misses.
You may be able to use "huge pages" for your workload, which
can use the 2/4MB pages. There is some good documentation for
it in Documentation/vm/ (and probably on the web).
--
SUSE Labs, Novell Inc.
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