Re: 2.6.12-rc5 is broken in nvidia Ck804 Opteron MB/with dual cor e dual way

["Siddha, Suresh B" <suresh.b.siddha@intel.com>]

On Fri, Jun 03, 2005 at 06:09:32PM +0200, Andi Kleen wrote:
> On Thu, Jun 02, 2005 at 01:42:00PM -0700, YhLu wrote:
> > 
> > for Intel it would be 
> > 	c->x86_num_cores  is 2 and smp_num_siblings is 2 too....
> > 	so every core will be HT....
> 
> If that was true, then a true DC+HT machine would report 4.
> 
> I doubt it is, but Suresh can probably clarify.

On  a DC+HT, x86_num_cores will be 2 and kernel will set smp_num_siblings 
to 2 (even though number of logical processors per physical package as
seen by cpuid.1.EBX.bits[23:16] will be 4).
Remember, smp_num_siblings in kernel will just represent HT logical siblings.

If CPU is just DC capable, cpuid.1.EBX.bits[23:16] will return '2' and
number of cores computation from cpuid.4.EAX.bits[31:26] will be 2. 
And kernel will set x86_num_cores to 2 and smp_num_siblings will be set to 1

If CPU is just HT capable,cpuid.1.EBX.bits[23:16] will return '2' and
number of cores computation from cpuid.4.EAX.bits[31:26] will be 1.
And kernel will set x86_num_cores to 1 and smp_num_siblings will be set to 2.

> > Function 0000_0001[EBX]
> > EBX[23:16] Logical Processor Count. If CPUID Fn[8000_0001, 0000_0001][EDX:
> > HTT, ECX:
> > CMPLegacy] = 11b, then this field indicates the number of CPU cores in the
> > processor.
> > Otherwise, this field is reserved.
> > 
> > what is intel value about cpuid(1) ebx [23:16], when the CPU is dual core,
> > but HT is disabled.
> > 1?

If CPU is DC+HT capable, but HT is disabled in bios, cpuid.1.EBX.bits[23:16] 
will still be 4 and during bootup, kernel will figure out that no HT
siblings came up and will reset smp_num_siblings to 1.

I am planning to do more cleanup post 2.6.12, so that smp_num_siblings will
be moved to per cpuinfo.

thanks,
suresh
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