On Wed, 1 Jun 2005, David Brownell wrote:
> On Wednesday 01 June 2005 3:33 pm, Rene Herman wrote:
> > Rene Herman wrote:
> >
> > > David Brownell wrote:
> >
> > >> The experiment: verify that only the RUN bit is set on your machine
> > >> too. If "Periodic" and/or "Async" bits are set, then the controller
> > >> is _supposed_ to be issuing DMA transfers over PCI, so less bandwidth
> > >> will be available. Otherwise, not.
> >
> > [ snip ]
> >
> > > and one after switching on the USB2 HDD, when the hdparm result for hda
> > > has dropped to 42 MB/s:
> > >
> > > ===
> > > bus pci, device 0000:00:09.2 (driver 10 Dec 2004)
> > > EHCI 1.00, hcd state 1
> > > structural params 0x00002204
> > > capability params 0x00006872
> > > status a008 Async Recl FLR
> >
> > Only see that "Async" now while rereading. Did you mean that one? If so,
> > I'm right now catting the registers file and that "Async" is toggling on
> > and off continuously. 4 cats in a row:
> >
> > status 0008 FLR
> > status 8008 Async FLR
> > status a008 Async Recl FLR
> > status 0008 FLR
>
> Tbat's strange ... shouldn't do that unless someone's issuing
> requests to the bus. Which shouldn't happen if no devices are
> hooked up to that bus. If the "command" register isn't turning
> on async requests, that's particularly strange.
>
> - Dave
Hi
Didn't you just forget to set H-bit in exactly one queue head? If there's
no entry with H-bit set, controller will loop over list of empty heads
again and again.
Mikulas
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