On Sun, 3 Apr 2005 02:37:57 +0100
Matthew Wilcox <[email protected]> wrote:
> My thought on this is that we should encode the endianness of the
> registers in the ioremap cookie. Some architectures (sparc, I think?) can
> do this in their PTEs. The rest of us can do it in our ioread/writeN
> methods. I've planned for this in the parisc iomap implementation but
> not actually implemented it.
SPARC64 can do it in the PTEs, but we just use raw physical
addresses in our I/O accessors, and in those load/store instructions
we can specify the endianness.
Be careful though. Endianness can be dealt with on a hardware
level. Consider a byte access to a 32-bit word sized config space
datum, the PCI controller on a big-endian system will likely byte-twist
the data lanes in order for this to work properly.
It's a subtle issue, and it's explained pretty well in some of the
UltraSPARC PCI controller docs at:
http://www.sun.com/processors/documentation.html
In particular, "U2P UPA to PCI User's Manual", chapter 10
"Little-Endian Support", has some informative diagrams.
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