Greg Felix wrote:
00:1f.2 Class 0101: 8086:27c0 (prog-if 8f [Master SecP SecO PriP PriO])
Subsystem: 103c:3011
Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium
TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 0
Interrupt: pin B routed to IRQ 5
Region 0: I/O ports at 10d8 [size=8]
Region 1: I/O ports at 10f0 [size=4]
Region 2: I/O ports at 10e0 [size=8]
Region 3: I/O ports at 10f4 [size=4]
Region 4: I/O ports at 10b0 [size=16]
Region 5: Memory at e04c4400 (32-bit, non-prefetchable)
[disabled] [size=1K]
I was hoping that we could detect when this PCI BAR is disabled, and
base the logic on that. But it appears that's not feasible for some BIOSen.
I suppose your patch is the best we can do.
Jeff
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