Could you please confirm that I understand correctly what is in the:
Dual-Core Update to the Intel Itanium 2 Processor Reference Manual...
"188.8.131.52 L2 Caches
Any coherence request to identify whether a cache line is in the processor
will invalidate that line from the L2I cache."
This makes sure that the DMAs invalidate the L2L cache.
"2.7.4 Instruction Cache Coherence Optimization
Coherence requests of the L1I and L2I caches will invalidate the line if
it is in the cache. Montecito allows instruction requests on the system
interface to be filtered such that they will not initiate coherence
requests of the L1I and L2I caches. This will allow instructions to be
cached at the L1I and L2I levels across multiple processors in a coherent
domain. This optimization is enabled by default, but may be disabled by
PAL_SET_PROC_FEATURES bit 5 of the Montecito feature_set (18)."
Machines star up whit bit 5 = 0, reading instruction pages via
NFS has to flush them from L2I.
I was wondering if instead of modifying do_no_page() and Co., should
not we make nfs_readpage() be DMA-like?
(No possible regression for most of the page I/O-s.)
I.e. it should be the responsibility of a file system to make sure it
supports instruction pages correctly. The base kernel should provide
such file systems with an architecture dependent macro...
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