Arjan, thank you very much for reviewing the driver.
Arjan van de Ven wrote:
On Sun, 2007-01-21 at 15:06 -0600, Jay Cliburn wrote:
[snip]
+void atl1_irq_disable(struct atl1_adapter *adapter)
+{
+ atomic_inc(&adapter->irq_sem);
+ iowrite32(0, adapter->hw.hw_addr + REG_IMR);
+ synchronize_irq(adapter->pdev->irq);
+}
doesn't this want a PCI posting flush?
I'm also a bit sceptical about irq_sem ...
PCI posting flush will be added. Would you mind elaborating on your
skepticism about irq_sem?
+/**
+ * When ACPI resume on some VIA MotherBoard, the Interrupt Disable bit/0x400
+ * on PCI Command register is disable.
+ * The function enable this bit.
+ * Brackett, 2006/03/15
+ */
+static void atl1_via_workaround(struct atl1_adapter *adapter)
+{
+ unsigned long value;
+
+ value = ioread16(adapter->hw.hw_addr + PCI_COMMAND);
+ if (value & PCI_COMMAND_INTX_DISABLE)
+ value &= ~PCI_COMMAND_INTX_DISABLE;
+ iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND);
+}
hmm I wonder if this shouldn't be a more generic PCI level quirk, not so
much a driver level quirk...
The vendor put this code here, and we're loathe to remove it unless
absolutely necessary. Is it okay with you if we leave it?
Thanks,
Jay
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