On Thu, Jan 18, 2007 at 09:14:06AM +0100, Martin Mares wrote:
> Hello!
>
> > I recommend we just delete the pci_bus class. I don't think it serves
> > any useful purpose. The bridge can be inferred frmo the sysfs hierarchy
> > (not to mention lspci will tell you). The cpuaffinity file should be
> > moved from the bus to the device -- it really doesn't make any sense to
> > talk about which cpu a bus is affine to, only a device.
>
> It doesn't seem to serve any useful purpose other than the affinity now,
> but I still think that it conceptually belongs there, because it makes
> sense to have per-bus attributes. For example, in the future we could
> show data width and signalling speed.
Other per bus attributes might be address routing, VGA routing enabled,
Fast-back-to-back enabled. PCI-X bridges and PCI-e bridges might also
advertise data related to MMRBC and similar onboard buffer mgt behaviors.
ISTR, IBM PCI-X bridge works better with 512 "block" (data xfer size)
than larger sizes becuase it internally allocates buffer space
in 512B chunks. It would be useful to know along with downstream
device MMRBC. Not sure this all has to come from /sys though.
grant
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