David Vrabel <[email protected]> :
[...]
> It was clocking the MII management interface (MDC) at 500 Hz so each PHY
> register access took some 130 ms, and many registers accesses were being
> done on initialization. According to the datasheet, the maximum
> frequency for MDC is 2.5 MHz. Delays have been adjusted accordingly.
[...]
> Index: linux-source-2.6.16/drivers/net/ipg.h
> ===================================================================
> --- linux-source-2.6.16.orig/drivers/net/ipg.h 2006-05-01 12:08:58.343035854 +0100
> +++ linux-source-2.6.16/drivers/net/ipg.h 2006-05-01 12:09:37.282602113 +0100
> @@ -672,10 +672,10 @@
> /* Number of IPG_AC_RESETWAIT timeperiods before declaring timeout. */
> #define IPG_AC_RESET_TIMEOUT 0x0A
>
> -/* Minimum number of miliseconds used to toggle MDC clock during
> +/* Minimum number of nanoseconds used to toggle MDC clock during
> * MII/GMII register access.
> */
> -#define IPG_PC_PHYCTRLWAIT 0x01
> +#define IPG_PC_PHYCTRLWAIT_NS 200
I would have expected a cycle of 400 ns (p.72/77 of the datasheet)
for a 2.5 MHz clock. Why is it cut by a two factor ?
--
Ueimor
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