Christoph Lameter wrote on Thursday, March 30, 2006 7:12 PM
> > On ia64, we map the following:
> > #define Smp_mb__before_clear_bit do { } while (0)
> > #define clear_bit clear_bit_mode(..., RELEASE)
> >
> > Which looked perfect fine to me. I don't understand why you say it does
> > not provide memory ordering.
>
> It does not provide a memory barrier / fence. Later memory references can
> still be moved by the processor above the instruction with release semantics.
That is perfect legitimate, and was precisely the reason for the invention of
smp_mb__after_clear_bit - prevent later load to leak before clear_bit.
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