From: Hollis Blanchard <[email protected]>
Date: Fri, 3 Mar 2006 15:18:13 -0600
> On Friday 03 March 2006 15:06, Benjamin Herrenschmidt wrote:
> > The main problem I've had in the past with the ppc barriers is more a
> > subtle thing in the spec that unfortunately was taken to the word by
> > implementors, and is that the simple write barrier (eieio) will only
> > order within the same storage space, that is will not order between
> > cacheable and non-cacheable storage.
>
> I've heard Sparc has the same issue... in which case it may not be a "chip
> designer was too literal" thing, but rather it really simplifies chip
> implementation to do it that way.
There is a "membar #MemIssue" that is meant to deal with this should
it ever matter, but for most sparc64 chips it doesn't which is why we
don't use that memory barrier type at all in the Linux kernel.
For UltraSPARC-I and II it technically could matter in Relaxed Memory
Ordering (RMO) mode which is what we run the kernel and 64-bit
userspace in, but I've never seen an issue resulting from it.
For UltraSPARC-III and later, the chip only implements the Total Store
Ordering (TSO) memory model and the manual explicitly states that
cacheable and non-cacheable memory operations are ordered, even using
language such as "there is an implicit 'membar #MemIssue' between
them". It further goes on to say:
The UltraSPARCIII Cu processor maintains ordering between
cacheable and non-cacheable accesses. The UltraSPARC III Cu
processor maintains TSO ordering between memory references
regardless of their cacheability.
Niagara behaves almost identically to UltraSPARC-III in this area.
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