On Wed, Nov 23, 2005 at 05:21:29PM +0000, Alan Cox wrote:
> On Mer, 2005-11-23 at 17:39 +0100, Andi Kleen wrote:
> > I much prefer the MSR bit too. Unfortunately it doesn't exist
> > (or rather I bet it exists somewhere, just undocumented) on Intel
> > systems.
>
> The MSR bits will break things like ECC scrubbing however. That can be
You mean it might break an insane hack in someone's ECC scrubbing
implementation. But last time I talked to people about this
they suggested just using an uncacheable mapping instead of
this horrible thing. Uncached is actually what you want there,
not relying on some undocumented lock bus cycle behaviour.
IMHO that would be much better and actually
have a chance of working over multiple generation.
> Certainly it would be cleaner and easier to save the MSR, scrub and put
> it back than do the fixup magic. Some drivers would need auditing as
> they seem to use locked ops or xchg (implicit lock) to lock with a PCI
> DMA master.
Which drivers? I don't think there is anything in tree. I went
over all the drivers early in the x86-64 port.
I'm sure I would have noticed because they very likely needed inline
assembly for this and this generally broke when moving to x86-64.
DRM did some tricks, but generally not with the hardware I believe,
only between user/kernel space.
-Andi
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