Johannes Stezenbach <[email protected]> wrote:
>
> From: Patrick Boettcher <[email protected]>
>
> Add big-endian register definitions for running on a PowerPC.
> (Thanks to Paavo Hartikainen for testing.)
>
> ...
> + struct {
> + u32 dma_address0 :30;
> + u32 dma_0No_update : 1;
> + u32 dma_0start : 1;
> + } dma_0x0;
>...
> +
> + struct {
> + u32 dma_0start : 1;
> + u32 dma_0No_update : 1;
> + u32 dma_address0 :30;
> + } dma_0x0;
Oh dear. This is a good demonstration of the downside of trying to use
compiler bitfields to represent hardware registers. I have vague memories
of writing BFINS and BFEXT in 3c59x to stomp this problem.
I don't think there's any guarantee that the code you have there will work
on all architectures/compiler versions btw.
Also... The code appears to be assuming that BE architectures will
bit-reverse their bitfields. Is that right? I'd expect them to only
byte-reverse them?
IOW:
31 30 ... 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
|--------------- dma_address0 --------------------|
| dma_0No_update
| dma_0start
versus
31 30 29 28 27 26 25 24 23 ... 08 07 06 05 04 03 02 01 00
|--------------| dma_address0
|---- more of dma_address0 -----|
| dma_0No_update
| dma_0start
or something like that... Brain hurts.
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